Board-level chip interconnection technology based on SRIO protocol

This article introduces this high-speed real-time data processing hardware platform based on SRIO interconnection technology, and on this platform, the SRIO communication technology between multiple DSPs and between DSP and FPGA is studied.

1 SRIO standard

RapiclI / O is a new generation of high-speed interconnection technology proposed for embedded system development with high reliability, high performance, and packet switching. It was approved by the International Organization for Standardization (ISO) and the International Electrotechnical Commission (IEC) as ISO / IECDIS in 2004 18372 standard. SRIO is a serial RapidIO interface for serial backplane, DSP and related serial data plane connection applications. Serial RapidIO contains a three-layer protocol, namely the physical layer, transport layer, and logical layer. The physical layer defines electrical characteristics, link control, and low-level error management; the transport layer defines packet switching, routing, and addressing mechanisms; and the logical layer defines the overall protocol and packet format. Can achieve the lowest pin count, adopt DMA transmission, support complex scalable topology, multi-point transmission; optional 1.25 Gbps, 2.5 Gbps, 3.125 Gbps three speeds can meet different application needs, is embedded in the next decade One of the best options for system interconnection.

2 Interconnection system based on C6455 high-speed SRIO interface

2.1 SRIO port of C6455

TMS320C6455 (referred to as C6455 for short) is a new DSP product from Texas Instruments (TD), which can achieve higher performance, streamline code, more on-chip memory and ultra-high bandwidth integrated peripherals. The most notable among them is the first The SRIO bus used for inter-processor communication has been implemented. The SRIO port on the C6455 is an interconnection scheme with a high number rate and few pins introduced for the embedded field. The data transmission of Rapicl I / O is entirely hardware The implementation does not require the participation of the processor, so this can realize an efficient board-level homogeneous interconnect multiprocessor system. The pair of SRIO ports of the C6455 sends and receives differential signal pairs to form a full-duplex port (port), which can work at 1.25 Gbps, 2.5 Gbps, 3.125 Gbps baud rate.

2.2 Multi-C6455 interconnection structure based on SRIO

The SRIO port of C6455 can be interconnected with SRIO switching devices, or it can be realized by connecting differential signals between C6455. As shown in the interconnection relationship between the 1x mode and the 4x mode shown in Figures 1 and 2, in the 1x mode, any pair of transmit and receive signals of the device can be connected to the transmit and receive signals of another device to form an independent 1x mode of operation. If four pairs of full connections are used between two C6455s, one 4x working mode or four independent 1x working modes can be realized.

The multi-DSP and FPGA parallel processing system is mainly composed of 4 C6455 processors and 4 Virtex5LX50T. The system structure is shown in Figure 3. The interconnection between DSP and DSP adopts the connection mode shown in Figure 1 to realize a fully connected SRIO network, and realizes one 1x channel between all DSPs, and the control and transmission on each channel work independently and in parallel. Through the SRIO interconnection network, any DSP C6455 can access other DSPC6455 resources on the network to achieve the sharing of all device resources on the network. Moreover, such a fully connected structure can be flexibly configured into a daisy-chain serial pipeline, a master-slave star, and other topologies according to the characteristics of different task processing. It has a high degree of dynamic reconfiguration in different data processing applications.

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