From Multicore to Many-Core: Architecture and Experience

You may be accustomed to the concept of the mulTIcore processor of the chip system (SoC), but the reality is always changing. In the Hot Chips conference held in August, it has been clearly stated that mulTIcore is developing to many-core: at the core of SoC, the number of closely related processor cores is increasing, from 2 or 4 to 8. 16 or even many, many.

This growth is only another stage of the development of Moore's Law. Can system developers clearly understand this? Is the change from mulTIcore to many-core a type change, or just a change in scale? Can this transformation solve the problems faced by system developers?

To find answers to these questions, we talked to a number of teams who have accumulated some design experience in many-core SoC development. We asked them a simple question: Is your experience different from using mulTIcore? For this simple question, we got a variety of answers.

The development of Many-core

The Hot Chips paper lists three main lines of development for the SoC architecture to the many-core field. We begin with the route described by Cavium's Kin-Yip Liu in a small-scale wireless base station SoC design paper that includes micro base stations, pico base stations, and femto base stations.

The design called Octeon Fusion CNF71xx is shown in Figure 1. It consists of two processing clusters, four sets of enhanced MIPS64 cores, and various hardware accelerators around a shared L2 cache, and six groups. Digital signal processing (DSP) cores, each with a number of hardware accelerators distributed around a shared memory switching fabric.

Figure 1. Cavium's Octeon Fusion architecture combines CPU clusters with connected hardware accelerators and discrete DSP core clusters.