Want to be a familiar PCB, you must see this 96 points!

Choosing PCB circuit boards must strike a balance between meeting design requirements and mass production and cost. Design requirements include both electrical and institutional components. This material problem is usually more important when designing very high speed PCB boards (greater than GHz). For example, the commonly used FR-4 material, the dielectric loss at a frequency of several GHz has a great influence on the signal attenuation, and may not be useful. As far as electrical is concerned, it is important to note whether the dielectric constant and the dielectric loss are combined at the designed frequency.

The basic idea of ​​avoiding high-frequency interference is to minimize the interference of high-frequency signal electromagnetic fields, which is called crosstalk. You can use the distance between the high-speed signal and the analog signal, or add ground guard/shunt traces next to the analog signal. Also pay attention to the digital ground noise interference to the analog ground.

Signal integrity is basically a matter of impedance matching. The factors affecting the impedance matching are the architecture of the signal source and the output impedance, the characteristic impedance of the trace, the characteristics of the load end, and the topology of the trace. The solution is to *terminate (terminaTIon) and adjust the topology of the trace.

There are two points to note for the wiring of the differential pair. One is that the length of the two lines should be as long as possible, and the other is that the spacing between the two lines (which is determined by the differential impedance) should remain the same, that is, to be parallel. There are two ways of paralleling. One is that the two lines are on the same side-by-side, and the other is two lines that are on the top-by-side. In general, the former side-by-side implementation is more.

To use differential routing, it must be meaningful that both the source and the receiver are differential signals. Therefore, differential wiring cannot be used for a clock signal with only one output.

The matching resistance between the differential pair of the receiving end is usually added, and its value should be equal to the value of the differential impedance. This signal quality will be better.

The wiring of the differential pairs should be properly close and parallel. The proper proximity is because this spacing affects the value of the differential impedance (differentTIal impedance), which is an important parameter for designing differential pairs. Parallelism is also required because the consistency of the differential impedance is maintained. If the two lines are too close, the differential impedance will be inconsistent, which will affect signal integrity and TIming delay.

(1) Basically, it is correct to isolate the analog/digital divisions. It should be noted that the signal trace should not cross the moat as much as possible, and do not let the return current path of the power supply and signal become too large.

(2) The crystal oscillator is an analog positive feedback oscillator circuit. To have a stable oscillation signal, the loop gain and phase specifications must be met. The oscillation specifications of the analog signal are easily disturbed, even if the ground guard traces may not be completely isolated. interference. And too far away, the noise on the ground plane will also affect the positive feedback oscillator circuit. Therefore, the distance between the crystal and the chip must be close to possible.

(3) There are many conflicts between high-speed wiring and EMI requirements. However, the basic principle is that the electrical resistance of the EMI or the ferrite bead cannot cause some electrical characteristics of the signal to fail to meet the specifications. Therefore, it is best to use the techniques of routing and PCB stacking to solve or reduce EMI problems, such as high-speed signals going inside. Finally, use resistors or ferrite bead to reduce the damage to the signal.

Most of the autorouters of the current wiring software have set constraints to control the winding method and the number of vias. The EDA company's winding engine capabilities and constraints are sometimes far from being set. For example, is there a sufficient constraint to control the way serpentine (蜿蜒), whether it can control the spacing of the differential pairs, and so on. This will affect whether the routing method that is automatically routed can meet the designer's ideas. In addition, the difficulty of manually adjusting the wiring is also absolutely related to the ability of the winding engine. For example, the ability to push the line, the ability to push through the hole, and even the ability to push the copper to the copper. Therefore, choosing a router with a strong winding engine is the solution.

The test coupon is used to measure the characteristic impedance of the PCB produced by TDR (Time Domain Reflectometer) to meet the design requirements. Generally, the impedance to be controlled has a single line and a differential pair. Therefore, the trace line width and line spacing (with differential pairs) on the test coupon should be the same as the line to be controlled. The most important thing is the position of the grounding point when measuring. In order to reduce the inductance of the ground lead, the TDR probe is usually grounded very close to the probe tip, so the distance and way of measuring the signal's point to the ground point on the test coupon To match the probe used.

Generally, most of the copper in the blank area is grounded. Just pay attention to the distance between the copper and the signal line when applying copper next to the high-speed signal line, because the copper applied will reduce the characteristic impedance of the trace. Also be careful not to affect the characteristic impedance of its layer, such as in the structure of a dual stripline.

Yes, both the power plane and the ground plane must be considered as reference planes when calculating the characteristic impedance. For example, a four-layer board: top layer - power layer - ground layer - bottom layer, then the model of the top trace characteristic impedance is a microstrip line model with the power plane as a reference plane.

Whether the general software automatically generates test points to meet the test requirements must see whether the specifications of the test points meet the requirements of the test equipment. In addition, if the wiring is too dense and the specification of the test points is strict, there may be no way to automatically add test points to each line. Of course, it is necessary to manually fill in the places to be tested.

As for whether it will affect the signal quality, it depends on how the test points are added and how fast the signal is. Basically add test points (without vias or DIP pins as test points) may be added online or pulled a short line from the line. The former is equivalent to adding a small capacitor on the line, while the latter is a branch. Both of these conditions will affect the high-speed signal more or less, and the degree of influence is related to the frequency speed of the signal and the edge rate of the signal. The size of the impact can be seen through simulation. In principle, the smaller the test point, the better (and of course the requirements of the test tool). The shorter the branch, the better.

When the signal or power supply between the PCB boards is connected, for example, the A board has power or signal sent to the B board, there must be an equal amount of current flowing from the ground to the A board (this is the Kirchoff current law). The current on this formation will flow back where the impedance is the least. Therefore, at each interface where the power source or signal is connected to each other, the number of pins allocated to the ground layer should not be too small to reduce the impedance, which can reduce the noise on the ground layer. In addition, you can also analyze the entire current loop, especially the larger current, adjust the ground or ground connection to control the current travel (for example, make a low impedance somewhere, let most of the current from this Place to reduce the impact on other sensitive signals.

Applications for high-speed digital circuits today include communications networks and computers. In terms of communication networks, the working frequency of the PCB has reached GHz, and the number of layers is as much as I know by 40 layers. Computer-related applications are also due to advances in chips. Whether it is a general PC or a server, the maximum operating frequency on the board has reached 400MHz (such as Rambus). In response to this high-speed, high-density wiring requirement, the demand for blind/buried vias, mircrovias, and build-up process processes is also increasing. These design requirements are available to manufacturers in large quantities.

a. microstrip line (microstrip)

Z={87/[sqrt(Er+1.41)]}ln[5.98H/(0.8W+T)] where W is the line width, T is the copper thickness of the trace, and H is the trace to the reference plane Distance, Er is the dielectric constant of the PCB material. This formula must be applied in the case of 0.1 (W/H) 2.0 and 1 (Er).

b. Stripline

Z=[60/sqrt(Er)]ln{4H/[0.67Ï€(T+0.8W)]} where H is the distance between the two reference planes, and the trace is in the middle of the two reference planes. This formula must be applied in the case of W/H "0.35 and T/H" 0.25.

In the middle of the differential signal, the ground line cannot be added. Because the most important point of application of differential signals is the benefits of mutual coupling between differential signals, such as flux cancellation, noise immunity, and the like. If the ground wire is added in the middle, the coupling effect will be destroyed.

A flexible printed circuit can be designed using software that generally designs PCBs. The same is produced in the Gerber format for FPC manufacturers. Because the manufacturing process is different from the general PCB, each manufacturer will have restrictions on the minimum line width, minimum line spacing, and minimum aperture depending on their manufacturing capabilities. In addition, some copper can be reinforced at the turning point of the flexible circuit board. As for the manufacturer of the product, the online "FPC" can be found as a keyword query.

The principle of selecting the PCB and case ground point selection is to use chassis ground to provide a low impedance path to the return current and the path to control this return current. For example, the ground plane of the PCB can be connected to the chassis ground by a fixed screw near the high-frequency device or the clock generator to minimize the entire current loop area and reduce electromagnetic radiation.

In the case of digital circuits, first determine three things in order:

1. Verify that all power supply values ​​are as designed. Some systems with multiple power supplies may require some specification of the order and speed of some power supplies.

2. Verify that all clock signal frequencies are working properly and that there are no non-monotonic problems on the edges of the signal.

3. Confirm that the reset signal meets the specifications.

If these are normal, the chip should signal the first cycle. Next, follow the system operation principle and the bus protocol to debug.

Crosstalk interference is of particular concern when designing high-speed, high-density PCBs because it has a large impact on timing and signal integrity. Here are a few caveats:

1. Control the continuity and matching of the characteristic impedance of the trace.

2. The size of the trace spacing. The spacing commonly seen is twice the line width. The simulation can be used to know the influence of the trace spacing on timing and signal integrity, and to find the minimum tolerance that can be tolerated. The results of different chip signals may vary.

3. Select the appropriate termination method.

4. Avoid the same direction of the upper and lower adjacent layers, even if the traces are just overlapping up and down, because this crosstalk is larger than the adjacent lines in the same layer.

5. Use blind/buried via to increase the area of ​​the trace. However, the manufacturing cost of the PCB board will increase.

It is really difficult to achieve full parallelism and equal length in actual implementation, but still try to do it. In addition, differential termination and common-mode termination can be reserved to mitigate the effects on timing and signal integrity.

The comparison of the LC and RC filtering effects must consider whether the selection of the frequency band and inductance value to be filtered is appropriate. Because the inductance of the inductor is related to the inductance value and frequency. If the noise frequency of the power supply is low and the inductance value is not large enough, the filtering effect may not be as good as RC. However, the cost of using RC filtering is that the resistor itself consumes energy, is inefficient, and pays attention to the power that the selected resistor can withstand.

In addition to considering the noise frequency that you want to filter out, you should consider the response capability of the instantaneous current. If the output of the LC has a chance to output a large current instantaneously, the large value of the inductor will hinder the speed at which this large current flows through the inductor and increase the ripple noise.

The value of the capacitor is related to the magnitude of the ripple noise specification that can be tolerated. The smaller the ripple noise value is, the larger the capacitance value will be. The ESR/ESL of the capacitor also has an effect.

In addition, if the LC is placed at the output of the switching regulation power, pay attention to the influence of the pole/zero generated by the LC on the loop stability of the negative feedback control. .

The increase in cost due to EMC on the PCB is usually due to an increase in the number of formations to enhance the shielding effect and increase the suppression of high frequency harmonic devices such as ferrite bead and choke. In addition, it is usually necessary to match the shielding structure of other mechanisms to make the whole system pass the EMC requirements. The following is only a few of the PCB design techniques to provide electromagnetic radiation effects that reduce the circuit.

1. Use devices with slower slew rate as much as possible to reduce the high frequency components generated by the signal. 2, pay attention to the position of the high-frequency device placement, not too close to the external connector.

3. Pay attention to the impedance matching of the high-speed signal, the trace layer and its return current path to reduce the high-frequency reflection and radiation.

4. Place enough decoupling capacitors on the power pins of each device to mitigate noise on the power plane and ground plane. Pay particular attention to whether the frequency response and temperature characteristics of the capacitor meet the design requirements.

5. The ground near the external connector can be properly segmented with the ground plane and the ground of the connector is connected to the chassis ground.

6, the appropriate use of ground guard / shunt traces next to some special high-speed signals. But pay attention to the effect of guard/shunt traces on the trace characteristic impedance.

7. The power supply layer is 20H smaller than the ground layer, and H is the distance between the power supply layer and the ground layer.

The reason for separating the digital/analog ground is because the digital circuit generates noise at the power supply and ground when switching between high and low potentials, and the magnitude of the noise is related to the speed and current of the signal. If the ground plane is not divided and the noise generated by the digital area circuit is large and the circuits of the analog area are very close, the analog signal will still be disturbed by the ground noise even if the digital-to-analog signal does not intersect. That is to say, the method of digitally undivided can only be used when the analog circuit area is far away from the digital circuit area where large noise is generated.

The requirement that the digital-to-analog signal trace cannot be crossed is because the digital signal whose speed is slightly faster will return to the source of the digital signal as much as possible along the ground near the lower line of the trace. When the line is crossed, the noise generated by the return current will appear in the analog circuit area.

Impedance matching is one of the design elements when designing high speed PCB circuits. The impedance value has an absolute relationship with the routing method, such as walking on the surface layer (microstrip) or inner layer (stripline/double stripline), distance from the reference layer (power layer or ground layer), trace width, PCB material, etc. Both will affect the characteristic impedance value of the trace. That is to say, the impedance value can be determined after wiring. General simulation software can not consider some non-continuous wiring conditions due to the limitation of the line model or the mathematical algorithm used. At this time, only some terminators, such as series resistors, can be reserved on the schematic. Moderate the effect of discontinuity in the trace impedance. The only way to solve the problem is to pay attention to avoiding impedance discontinuities.

The accuracy of the IBIS model directly affects the results of the simulation. Basically, IBIS can be regarded as the electrical characteristics of the actual chip I/O buffer equivalent circuit. It can be converted from SPICE model (can also be measured, but more limited), while SPICE data and chip manufacturing have absolute Relationship, so the same device is provided by different chip manufacturers, the SPICE data is different, and the data in the converted IBIS model will also vary. That is to say, if the devices of the A manufacturer are used, only they have the ability to provide accurate model data of their devices, because no one else knows better than them what process their devices are made of. If the IBIS provided by the manufacturer is inaccurate, it can only be solved by constantly asking the manufacturer to improve.

In general EMI/EMC design, both radiated and conducted aspects need to be considered. The former belongs to the higher frequency part ("30MHz) and the latter is the lower frequency part ("30MHz"). So you can't just pay attention to the high frequency and ignore the low frequency part.

A good EMI/EMC design must take into account the location of the device, the layout of the PCB stack, the important way of moving the device, the choice of the device, etc., if there is no better arrangement beforehand, and then solve it afterwards. It will do more with less and increase costs. For example, the position of the clock generator should be as close as possible to the external connector. The high-speed signal should go as far as possible to the inner layer and pay attention to the characteristic impedance matching and the continuity of the reference layer to reduce the reflection. The slope of the signal pushed by the device is as small as possible to reduce the reflection. For high frequency components, when decoupling/bypass capacitors are selected, pay attention to whether the frequency response meets the requirements to reduce the power layer noise. In addition, pay attention to the return path of the high-frequency signal current so that the loop area is as small as possible (that is, the loop impedance is as small as possible) to reduce the radiation. It is also possible to divide the formation to control the range of high frequency noise. Finally, properly select the chassis ground of the PCB and the enclosure.

In the current pcb design software, thermal analysis is not a strong point, so it is not recommended to use, other functions 1.3.4 can choose PADS or Cadence performance price ratio is good.

Beginners of PLD design can use the integrated environment provided by PLD chip manufacturers, and can use single point tools when designing more than one million gates.

With conventional circuit design, INNOVEDA's PADS is very good, and there are simulation software that works together, and this type of design often occupies 70% of applications. In high-speed circuit design, analog and digital hybrid circuits, Cadence's solution should be a relatively good performance software. Of course, Mentor's performance is still very good, especially its design process management should be the best. (Da Tang Telecom Technology Expert Wang Sheng)

Topoverlay ---- The top device name, also known as top silkscreen or top component legend, such as R1 C5, IC10.

Bottomoverlay----same reason

Multilayer-----If you design a 4-layer board, you place a free pad or via, define it as multilay, then its pad will automatically appear on 4 layers, if you only define it as top layer, then Its pad will only appear on the top layer.

High-frequency PCBs above 2G belong to RF circuit design and are not covered by high-speed digital circuit design. The layout and routing of the RF circuit should be considered together with the schematic, as the layout will cause a distribution effect. Moreover, the RF circuit design of some passive components is realized by parameterized definition, special shape copper foil, so EDA tools are required to provide parametric devices and to edit special shape copper foil.

Mentor's boardstation has dedicated RF design modules to meet these requirements. Moreover, the general RF design requires a special RF circuit analysis tool, the industry's most famous is agilent's eesoft, and Mentor's tools have a good interface.

RF microstrip line design requires 3D field analysis tools to extract transmission line parameters. All rules should be specified in this field extraction tool.

To ensure that the drive capability of the clock should not be achieved through protection, a clock driver chip is generally used. The general concern about clock drive capability is due to multiple clock loads. Using a clock driver chip, a clock signal is turned into several, using a point-to-point connection. Select the driver chip, in addition to ensuring a basic match with the load, the signal edge meets the requirements (generally the clock is along the valid signal). When calculating the system timing, it is necessary to count the clock delay in the driver chip.

The shorter the clock signal, the smaller the transmission line effect. Using a separate clock signal board increases the signal routing length. Moreover, the grounding power supply of the board is also a problem. For long distance transmission, a differential signal is recommended. The LVDS signal can meet the drive capability requirements, but your clock is not too fast and is not necessary.

If the third harmonic is large, the second harmonic is small, probably because the signal duty cycle is 50%, because in this case, the signal has no even harmonics. At this time, you need to modify the signal duty cycle.

In addition, for a clock signal that is unidirectional, source-side series matching is generally used. This suppresses secondary reflections but does not affect the clock edge rate. The source matching value can be obtained by the formula below.

Topology, some is also called routing order. The routing order for networks with multi-port connections.

This kind of network signal direction is more complicated, because the unidirectional, bidirectional signal, different level signal, the topology effect is different, it is difficult to say which topology is beneficial to the signal quality. Moreover, when doing pre-simulation, what kind of topology is used is very demanding for engineers, and it is required to understand the circuit principle, signal type, and even wiring difficulty.

First of all, EMI should be considered from the system, and the PCB alone cannot solve the problem.

For EMI, I think it is mainly to provide the shortest return path of the signal, reduce the coupling area, and suppress differential mode interference. In addition, the ground layer is tightly coupled to the power layer, which is more suitable than the power layer to suppress common mode interference.

There are several reasons for copper plating.

(1) EMC. For a large area of ​​ground or power copper, it will play a shielding role, and some special, such as PGND to protect.

(2) PCB process requirements. Generally, in order to ensure the plating effect, or the laminate is not deformed, copper is laid for the PCB layer with less wiring.

(3) Signal integrity requirements, giving a high-frequency digital signal a complete return path and reducing the wiring of the DC network. Of course, there are heat dissipation, special device installation requires copper plating and so on.

Look at the ratio of your signal rate to the length of the wiring. Signal integrity issues are considered if the delay of the signal on the transmission line and the time of the signal change are comparable. In addition, for multiple DSPs, clocks, data signal traces will also affect signal quality and timing, and need attention.

As for the tools, in addition to PROTEL, there are many wiring tools, such as MENTOR's WG2000, EN2000 series and powerpcb, Cadence's allegro, zuken's cadstar, cr5000, etc., each with its own strengths.

Signal return path, that is, return current. When a high-speed digital signal is transmitted, the signal flows from the driver along the PCB transmission line to the load, and then the load returns to the driver through the shortest path along the ground or power source. This return signal on the ground or power supply is called the signal return path. Dr. Johson explained in his book that high-frequency signal transmission is actually the process of charging the dielectric capacitor between the transmission line and the DC layer. SI analyzes the electromagnetic properties of this paddock and the coupling between them.

In the IBIS 3.2 specification, there is a description of the connector model. The EBD model is generally used. If it is a special board, such as a backplane, a SPICE model is required. Multi-board simulation software (HYPERLYNX or IS_multiboard) can also be used. When building a multi-board system, the distribution parameters of the input connectors are generally obtained from the connector manual. Of course, this method will not be accurate enough, but as long as it is within an acceptable range.

Terminal, also known as matching. The active end matching and the terminal matching are generally classified according to the matching position. The source-side matching is generally resistance series matching, and the terminal matching is generally parallel matching. There are many ways, such as resistance pull-up, resistance pull-down, Dyvenan matching, AC matching, and Schottky diode matching.

The matching mode is generally determined by the BUFFER characteristics, the topology, the type of the level, and the decision mode. The duty cycle of the signal and the power consumption of the system are also considered.

The most critical aspect of digital circuits is the timing problem. The purpose of the matching is to improve the signal quality and obtain a determinable signal at the decision time. For the level effective signal, the signal quality is stable under the premise of ensuring the establishment and holding time; for the delay effective signal, the signal change delay speed meets the requirements under the premise of ensuring the signal delay monotonicity. Some information about matching is available in the Mentor ICX product textbook. In addition, "High Speed ​​Digital design a hand book of blackmagic" has a chapter dedicated to the terminal, from the electromagnetic wave principle to describe the role of matching on signal integrity, for reference.

The IBIS model is a behavioral model and cannot be used for functional simulation. Functional simulation requires the use of SPICE models, or other structural level models.

It should be said that it is the same in principle. Because the power supply and ground are equivalent to high frequency signals.

The purpose of distinguishing the analog and digital parts is to prevent interference, mainly the interference of digital circuits to analog circuits. However, the segmentation may cause the signal return path to be incomplete, affecting the signal quality of the digital signal and affecting the system EMC quality. Therefore, no matter which plane is divided, it depends on whether the signal return path is increased and how much the recirculation signal interferes with the normal working signal.

There are also some hybrid designs, regardless of the power supply and ground. In the layout, the layout is separated according to the digital part and the analog part to avoid cross-region signals.

FCC: federal communication commission

EMC: electro megnetic compatibility

FCC is a standards organization and EMC is a standard. Standards are issued with corresponding reasons, standards and test methods.

Differential signals, some of which are also called differential signals, use two identical signals with opposite polarities to transmit one channel of data, and are judged according to the difference between the two signal levels. In order to ensure that the two signals are completely consistent, parallelism should be maintained during wiring, and the line width and line spacing remain unchanged.

There are many types of simulations, and high-speed digital circuit signal integrity analysis and simulation (SI) commonly used software are icx, signalvision, hyperlynx, XTK, speectraquest and so on. Some also use Hspice.

In high-speed digital circuits, in order to improve signal quality and reduce wiring difficulty, a multi-layer board is generally used to allocate a dedicated power layer and a ground layer.

The key to high-speed digital signal routing is to reduce the impact of the transmission line on signal quality. Therefore, the high-speed signal layout above 100M requires the signal trace to be as short as possible.

In digital circuits, high-speed signals are defined by the signal rise time. Moreover, different types of signals (such as TTL, GTL, LVTTL), the method of ensuring signal quality is different.

Hybrid circuit design is a big problem. It's hard to have a perfect solution.

Generally, the RF circuit is laid out as a separate single board in the system, and even a special shielding cavity is provided. Moreover, the RF circuit is generally single-sided or double-sided, and the circuit is relatively simple, all of which are designed to reduce the influence on the distribution parameters of the RF circuit and improve the consistency of the RF system. Compared with the general FR4 material, the RF circuit board tends to be a substrate with a high Q value. The dielectric constant of this material is relatively small, the transmission line distribution capacitance is small, the impedance is high, and the signal transmission delay is small.

In the hybrid circuit design, although the radio frequency and digital circuits are on the same PCB, they are generally divided into a radio frequency circuit area and a digital circuit area, and are respectively arranged and routed. Shielded between grounded vias and shielded boxes.

Mentor's board-level system design software, in addition to basic circuit design features, also has a dedicated RF design module. In the RF schematic design module, a parameterized device model is provided, and a bidirectional interface with an RF circuit analysis simulation tool such as EESOFT is provided; in the RF LAYOUT module, a pattern editing function dedicated to the layout of the RF circuit is provided, and The bidirectional interface of the RF circuit analysis simulation tool such as EESOFT can reverse the schematic and PCB for the analysis and simulation results. At the same time, using the design management function of Mentor software, design reuse, design derivation, and collaborative design can be easily realized. Greatly accelerate the hybrid circuit design process.

The mobile phone board is a typical hybrid circuit design, and many large mobile phone design manufacturers use Mentor plus Angeline's eesoft as a design platform.

Mentor Graphics' PCB tools are available in the WG (formerly veribest) series and the Enterprise (boardstation) series.

Mentor的autoactive RE由收购得来的veribest发展而来，是业界第一个无网格，任意角度布线器。

众所周知，对于球栅阵列，COB器件，无网格，任意角度布线器是解决布通率的关键。

在最新的autoactive RE中，新增添了推挤过孔，铜箔，REROUTE等功能，使它应用更方便。另外，他支持高速布线，包括有时延要求信号布线和差分对布线。

Mentor软件在定义好差分对属性后，两根差分对可以一起走线，严格保证差分对线宽，间距和长度差，遇到障碍可以自动分开，在换层时可以选择过孔方式。

一般说来，三个电源分别做在三层，对信号质量比较好。因为不大可能出现信号跨平面层分割现象。跨分割是影响信号质量很关键的一个因素，而仿真软件一般都忽略了它。

对于电源层和地层，对高频信号来说都是等效的。在实际中，除了考虑信号质量外，电源平面耦合（利用相邻地平面降低电源平面交流阻抗），层叠对称，都是需要考虑的因素。

很多PCB厂家在PCB加工完成出厂前，都要经过加电的网络通断测试，以确保所有联线正确。同时，越来越多的厂家也采用x光测试，检查蚀刻或层压时的一些故障。

对于贴片加工后的成品板，一般采用ICT测试检查，这需要在PCB设计时添加ICT测试点。如果出现问题，也可以通过一种特殊的X光检查设备排除是否加工原因造成故障。

是的。机壳要尽量严密，少用或不用导电材料，尽可能接地。

不论是双层板还是多层板，都应尽量增大地的面积。在选择芯片时要考虑芯片本身的ESD特性，这些在芯片说明中一般都有提到，而且即使不同厂家的同一种芯片性能也会有所不同。设计时多加注意，考虑的全面一点，做出电路板的性能也会得到一定的保证。但ESD的问题仍然可能出现，因此机构的防护对ESD的防护也是相当重要的。

在做PCB板的时候，一般来讲都要减小回路面积，以便减少干扰，布地线的时候，也不应布成闭合形式，而是布成树枝状较好，还有就是要尽可能增大地的面积。

如果可以采用分离电源当然较好，因为如此电源间不易产生干扰，但大部分设备是有具体要求的。既然仿真器和PCB板用的是两个电源，按我的想法是不该将其共地的。

一个电路由几块PCB构成，多半是要求共地的，因为在一个电路中用几个电源毕竟是不太实际的。但如果你有具体的条件，可以用不同电源当然干扰会小些。

手持产品又是金属外壳，ESD的问题一定比较明显，LCD也恐怕会出现较多的不良现象。如果没办法改变现有的金属材质，则建议在机构内部加上防电材料，加强PCB的地，同时想办法让LCD接地。当然，如何操作要看具体情况。

就一般的系统来讲，主要应考虑人体直接接触的部分，在电路上以及机构上进行适当的保护。至于ESD会对系统造成多大的影响，那还要依不同情况而定。干燥的环境下，ESD现象会比较严重，较敏感精细的系统，ESD的影响也会相对明显。虽然大的系统有时ESD影响并不明显，但设计时还是要多加注意，尽量防患于未然。

变化的信号（例如阶跃信号）沿传输线由A到B传播，传输线CD上会产生耦合信号，变化的信号一旦结束也就是信号恢复到稳定的直流电平时，耦合信号也就不存在了，因此串扰仅发生在信号跳变的过程当中，并且信号沿的变化（转换率）越快，产生的串扰也就越大。空间中耦合的电磁场可以提取为无数耦合电容和耦合电感的集合，其中由耦合电容产生的串扰信号在受害网络上可以分成前向串扰和反向串扰Sc，这个两个信号极性相同；由耦合电感产生的串扰信号也分成前向串扰和反向串扰SL，这两个信号极性相反。耦合电感电容产生的前向串扰和反向串扰同时存在，并且大小几乎相等，这样，在受害网络上的前向串扰信号由于极性相反，相互抵消，反向串扰极性相同，叠加增强。

串扰分析的模式通常包括默认模式，三态模式和最坏情况模式分析。默认模式类似我们实际对串扰测试的方式，即侵害网络驱动器由翻转信号驱动，受害网络驱动器保持初始状态（高电平或低电平），然后计算串扰值。这种方式对于单向信号的串扰分析比较有效。三态模式是指侵害网络驱动器由翻转信号驱动，受害的网络的三态终端置为高阻状态，来检测串扰大小。这种方式对双向或复杂拓朴网络比较有效。最坏情况分析是指将受害网络的驱动器保持初始状态，仿真器计算所有默认侵害网络对每一个受害网络的串扰的总和。这种方式一般只对个别关键网络进行分析，因为要计算的组合太多，仿真速度比较慢。

对于微波电路设计，地平面的面积对传输线的参数有影响。具体算法比较复杂（请参阅安杰伦的EESOFT有关资料）。而一般PCB数字电路的传输线仿真计算而言，地平面面积对传输线参数没有影响，或者说忽略影响。

EMC的三要素为辐射源，传播途径和受害体。传播途径分为空间辐射传播和电缆传导。所以要抑制谐波，首先看看它传播的途径。电源去耦是解决传导方式传播，此外，必要的匹配和屏蔽也是需要的。

铺地的作用有几个方面的考虑：1，屏蔽；2，散热；3，加固；4，PCB工艺加工需要。所以不管几层板铺地，首先要看它的主要原因。

这里我们主要讨论高速问题，所以主要说屏蔽作用。表面铺地对EMC有好处，但是铺铜要尽量完整，避免出现孤岛。一般如果表层器件布线较多。

很难保证铜箔完整，还会带来内层信号跨分割问题。所以建议表层器件或走线多的板子，不铺铜。

布线拓扑对信号完整性的影响，主要反映在各个节点上信号到达时刻不一致，反射信号同样到达某节点的时刻不一致，所以造成信号质量恶化。一般来讲，星型拓扑结构，可以通过控制同样长的几个stub，使信号传输和反射时延一致，达到比较好的信号质量。

在使用拓扑之间，要考虑到信号拓扑节点情况、实际工作原理和布线难度。不同的buffer，对于信号的反射影响也不一致，所以星型拓扑并不能很好解决上述数据地址总线连接到flash和sdram的时延，进而无法确保信号的质量；另一方面，高速的信号一般在dsp和sdram之间通信，flash加载时的速率并不高，所以在高速仿真时只要确保实际高速信号有效工作的节点处的波形，而无需关注flash处波形；星型拓扑比较菊花链等拓扑来讲，布线难度较大，尤其大量数据地址信号都采用星型拓扑时。

是否高速信号是依据信号上升沿而不是绝对频率或速度。自动或手动布线要看软件布线功能的支持，有些布线手工可能会优于自动布线，但有些布线，例如查分布线，总线时延补偿布线，自动布线的效果和效率会远高于手工布线。一般PCB基材主要由树脂和玻璃丝布混合构成，由于比例不同，介电常数和厚度都不同。一般树脂含量高的，介电常数越小，可以更薄。具体参数，可以向PCB生产厂家咨询。另外，随着新工艺出现，还有一些特殊材质的PCB板提供给诸如超厚背板或低损耗射频板需要。

划分地的目的主要是出于EMC的考虑，担心数字部分电源和地上的噪声会对其他信号，特别是模拟信号通过传导途径有干扰。至于信号的和保护地的划分，是因为EMC中ESD静放电的考虑，类似于我们生活中避雷针接地的作用。无论怎样分，最终的大地只有一个。只是噪声泻放途径不同而已。

是否加屏蔽地线要根据板上的串扰/EMI情况来决定，而且如对屏蔽地线的处理不好，有可能反而会使情况更糟。

对时钟线的布线，最好是进行信号完整性分析，制定相应的布线规则，并根据这些规则来进行布线。

如果是顶层放器件，底层布线。

跳线是PCB设计中特别的器件，只有两个焊盘，距离可以定长的，也可以是可变长度的。手工布线时可根据需要添加。板上会有直连线表示，料单中也会出现。

过孔上信号的回流路径现在还没有一个明确的说法，一般认为回流信号会从周围最近的接地或接电源的过孔处回流。一般EDA工具在仿真时都把过孔当作一个固定集总参数的RLC网络处理，事实上是取一个最坏情况的估计。

前仿真分析，可以得到一系列实现信号完整性的布局、布线策略。通常这些策略会转化成一些物理规则，约束PCB的布局和布线。通常的规则有拓扑规则，长度规则，阻抗规则，并行间距和并行长度规则等等。PCB工具可以在这些约束下，完成布线。当然，完成的效果如何，还需要经过后仿真验证才知道。

此外，Mentor提供的ICX支持互联综合，一边布线，一边仿真，实现一次通过。

选择PCB的软件，根据自己的需求。市面提供的高级软件很多，关键看看是否适合您设计能力，设计规模和设计约束的要求。刀快了好上手，太快会伤手。找个EDA厂商，请过去做个产品介绍，大家坐下来聊聊，不管买不买，都会有收获。

从PCB加工角度，一般将面积小于某个单位面积的铜箔叫碎铜，这些太小面积的铜箔会在加工时，由于蚀刻误差导致问题。从电气角度来讲，将没有合任何直流网络连结的铜箔叫浮铜，浮铜会由于周围信号影响，产生天线效应。浮铜可能会是碎铜，也可能是大面积的铜箔。

应该说侵害网络对受害网络造成的串扰与信号变化沿有关，变化越快，引起的串扰越大，（V=L*di/dt）。串扰对受害网络上数字信号的判决影响则与信号频率有关，频率越快，影响越大。详情请参阅相关链接：

具体讲，在PCB中使用机械层画邦定图，IC衬底衬根据IC SPEC.决定接vccgndfloat，用机械层print bonding drawing即可。

可以根据原理图对生成的网络表进行手工编辑， 检查通过后即可自动布线。用制板软件自动布局和布线的板面都不十分理想。网络表错误可能是没有指定原理图中元件封装；也可能是布电路板的库中没有包含指定原理图中全部元件封装。如果是单面板就不要用自动布线，双面板就可以用自动布线。也可以对电源和重要的信号线手动，其他的自动。

如果是清洁问题，可用专用的电器触点清洁剂清洗，或用写字用的橡皮擦清洁PCB。还要考虑1、金手指是否太薄，焊盘是否和插座不吻合；2、插座是否进了松香水或杂质；3、插座的质量是否可靠。

一个很好的问题。焊盘对高速信号有的影响，它的影响类似器件的封装对器件的影响上。详细的分析，信号从IC内出来以后，经过绑定线，管脚，封装外壳，焊盘，焊锡到达传输线，这个过程中的所有关节都会影响信号的质量。但是实际分析时，很难给出焊盘、焊锡加上管脚的具体参数。所以一般就用IBIS模型中的封装的参数将他们都概括了，当然这样的分析在较低的频率上分析是可以接收的，对于更高频率信号更高精度仿真，就不够精确了。现在的一个趋势是用IBIS的V －I、V－T曲线描述buffer特性，用SPICE模型描述封装参数。当然，在IC设计当中，也有信号完整性问题，在封装选择和管脚分配上也考虑了这些因素对信号质量的影响。

自动浮铜中出现的尖角浮铜问题，的确是各很麻烦的问题，除了有你提到的放电问题外，在加工中也会由于酸滴积聚问题，造成加工的问题。从2000年起， mentor在WG和EN当中，都支持动态铜箔边缘修复功能，还支持动态覆铜，可以自动解决你所提到的问题。请见动画演示。（如直接打开有问题，请按鼠标右键选择“在新窗口中打开”，或选择“目标另存为”将该文件下载到本地硬盘再打开。）

电源若作为平面层处理，其方式应该类似于地层的处理，当然，为了降低电源的共模辐射，建议内缩20倍的电源层距地层的高度。如果布线，建议走树状结构，注意避免电源环路问题。电源闭环会引起较大的共模辐射。

地址线是否要采用星型布线，取决于终端之间的时延要求是否满足系统的建立、保持时间，另外还要考虑到布线的难度。星型拓扑的原因是确保每个分支的时延和反射一致，所以星型连接中使用终端并联匹配，一般会在所有终端都添加匹配，只在一个分支添加匹配，不可能满足这样的要求。

正反贴的PCB设计，只要你的焊接加工没问题，当然可以。

150Mhz的时钟布线，要求尽量减小传输线长度，降低传输线对信号的影响。如果还不能满足要求，仿真一下，看看匹配、拓扑、阻抗控制等策略是有效。

答：一般的PCB的铜箔厚度为1盎司，约1.4mil的话，大致1mil线宽允许的最大电流为1A。过孔比较复杂，除了与过孔焊盘大小有关外，还与加工过程中电镀后孔壁沉铜厚度有关。